1. Technical Field of the Invention
This invention relates generally to data communications and more particularly to aligning and/or deskewing high-speed data and/or clock signals.
2. Description of Related Art
Communication systems are known to transport large amounts of data between a plurality of end user devices, which, for example, include telephones, facsimile machines, computers, television sets, cellular telephones, personal digital assistants, etc. As is also known, such communication systems may be local area networks (LANs) and/or wide area networks (WANs) that are stand-alone communication systems or interconnected to other LANs and/or WANs as part of a public switched telephone network (PSTN), packet switched data network (PSDN), integrated service digital network (ISDN), the Internet, etc. As is further known, communication systems include a plurality of system equipment to facilitate the transporting of data. Such system equipment includes, but is not limited to, routers, switches, bridges, gateways, protocol converters, frame relays, private branch exchanges, etc.
The transportation of data within communication systems is typically governed by one or more standards that ensure the integrity of data conveyances and fairness of access for data conveyances. For example, there are a variety of Ethernet standards that govern serial transmissions within a communication system at data rates of 10 megabits per second, 100 megabits per second, 1 gigabit per second and beyond. Another standard, which is for fiber optic data conveyances, is Synchronous Optical NETwork (SONET) that provides a data rate of 10 gigabits per second. In accordance with such standards, many system equipment components and end user devices of a communication system transport data via serial transmission paths. Internally, however, the system equipment components and end user devices process data in a parallel manner. As such, each system equipment component and end user device must receive the serial data and convert the serial data into parallel data without loss of information.
FIG. 1 is a schematic block diagram of integrated circuits that may be included in a system equipment component and/or in an end user device. As shown, a Field Programmable Gate Array (FPGA) 10 is coupled to a memory chip 12 and to a network chip 14. As is further shown, the connection between the FPGA 10 and the memory chip 12 includes a plurality of discontinuous parallel serial data streams and the connection between the connection between the FPGA 10 and the network chip 14 includes a plurality of parallel continuous serial data streams. As is known, the parallel serial data streams are used to increase data rates while maintaining compliance with serial transmission standards.
To process receiving of the plurality of discontinuous serial data streams, the FPGA 10 includes a plurality of discontinuous interfaces 16 and 18, and a plurality of continuous interfaces 20 and 22. In some embodiments, FPGA 10 may optionally include a plurality of serial to parallel modules 17A and B, and 21A and B (shown in dotted boxes in the figure). The discontinuous interfaces 16 and 18 each receive one of the plurality of discontinuous serial data streams and synchronizes the serial data stream to a local clock of the FPGA 10 and aligns the synchronized serial data stream with the synchronized serial data streams produced by the other discontinuous interfaces. The optional serial to parallel modules 17A and B convert the aligned and synchronized serial data streams into parallel data in accordance with the standard, or standards, to which the device is compliant.
The continuous interfaces 20 and 22 perform a similar function as discontinuous interfaces 16 and 18, but for the continuous data from the network chip 16. As such, the continuous interfaces 20 and 22 align and synchronize the continuous parallel serial data streams, which may then be converted into parallel data by the optional serial to parallel modules 21A and B. Due to the different nature of the continuous serial data streams and the discontinuous data streams, the continuous interfaces 20 and 22 cannot reliably be used for the discontinuous interfaces 16 and 18.
FIG. 2 is a schematic block diagram of a continuous interface 20 or 22 that includes a clock recovery module 26, a retiming unit 24, and a resynchronization unit 28. The clock recovery module 26 receives an incoming serial data stream, which is at a rate equal to the local clock or a fraction thereof, and re-aligns it based on the local clock to produce a recovered clock F2. The retiming unit 24 retimes the incoming data based on the recovered clock F2 to produce retimed data. The resynchronization unit 28 synchronizes the retimed data with the local clock to produce aligned and synced data.
While the continuous interface 20 or 22 works well for aligning and synchronizing continuous data streams, it does not reliably align and synchronize discontinuous data streams due to one or more of: a lack of a local reference clock (e.g., memory devices transmit a non-continuous strobe with the data), lack of continuous data, a requirement for a resynchronization block, and lack of programmability of the clock recovery module.
To increase the flexibility of use of an FPGA, or any other device that receives continuous and discontinuous data streams, it is desirable to have one interface that accurately aligns and deskews (or synchronizes) both continuous and discontinuous data streams.
Therefore, a need exists for a data alignment and deskewing module that accurately aligns and deskews (or synchronizes) both continuous and discontinuous data streams.